------------------------------------------------------------------------------- B O S T O N U N I V E R S I T Y Computer Science Department C O L L O Q U I U M Monday March 14, 1994 11:00am (Coffee served at 10:30am) Seminar Room / MCS 135 ------------------------------------------------------------------------------- The Evaluation of Massively Parallel Array Architectures Martin Herbordt University of Massachusetts Although massively parallel arrays have been proposed since the 1950's and built since the 1960's, there have been very few systematic empirical studies and these have covered only a small fraction of the design space. The major problems have been the computational cost of detailed and accurate simulations, the programming cost of creating a test suite that runs with comparable efficiency on diverse target architectures, and the lack of a realistic workload. We address the problem of computational cost with a novel approach to trace-based simulation. Code is run on an abstract virtual machine to generate a coarse-grained trace, which is then refined through a series of transformations wherein greater resolution is obtained with respect to the details of the target architecture. We have found this technique to be one to two orders of magnitude faster than detailed simulation, while still retaining much of the accuracy of the model. The trade-off between fairness to diverse target architectures and programmability of the test suite is addressed through the use of operator and application libraries for a small set of critical functions. We have found that failure to do this can result in unacceptably large errors, while the size of these libraries seems to be surprisingly manageable. A realistic workload consisting of a test suite of non-trivial spatially mapped application codes has been created. These programs are either parallel versions of existing applications of established utility, or products of collaboration with researchers in vision, robotics, and VLSI. I will also present some of the results obtained so far, including the relative benefits of different topologies in circuit switched networks, the effect of varying the dimensions in k-ary n-cubes, trade-offs in register file and cache design, and the usefulness of certain ALU features. These results are contributing to the design of the next generation of a system that has already had two generations of prototypes built at UMass. This research was funded, in part, by ARPA, the NSF, and an IBM Fellowship. Host: Prof. Steve Homer ------------------------------------------------------------------------------- For more information contact Prof. Azer Bestavros -------------------------------------------------------------------------------