Subject: IEEE-CS TC-RTS Newsletter for Sat Oct 21, 1995 _______________________________________________________________________________ __ _ __ ___ ___ __ __ I E E E Technical Committee |\ | |_ | | (_' | |_ | | |_ |_) C S on Real-Time Systems | \| |__ |/\| ,_) |__ |__ | | |__ | \ _______________________________________________________________________________ Table of Contents Line ----------------- ---- 1. best@cs.bu.edu (Azer Bestavros) (1599 lines) RTSS'95: Early Registration Deadline is almost here!............... 3 RTSS'95: Advance Program........................................... 16 RTSS'95: Abstracts of Technical Presentations...................... 591 RTDB'96: Call for papers........................................... 1456 2. lwelch%dorado@relay.nswc.navy.mil (Lonnie Welch) (175 lines) OORTS'96 Program................................................... 1602 3. Phillip C-Y Sheu (156 lines) WORDS96: Call for papers........................................... 1785 4. toda@etlca0.etl.go.jp (Kenji Toda) (560 lines) Advance Program & Information on RTCSA95, Japan.................... 1933 ------------------------------------------------------------------------------ <<<<<<<<<<<<<<<<<<* START OF THE IEEE-CS TC-RTS NEWSLETTER *>>>>>>>>>>>>>>>>>> ------------------------------------------------------------------------------ Message 1; Postmarked Wed Oct 11 11:24:26 1995 From: best@cs.bu.edu (Azer Bestavros) Subject: RTSS'95: Early Registration Deadline is almost here! Content-Length: 62891 This is a reminder that the November 1, 1995 Early Registration Deadline for the RTSS'95 Conference and Tutorials (as well as Hotel Accomodations) is fast approaching! The Advance program and the list of Presentation Abstracts are enclosed. --Azer Subject: RTSS'95: Advance Program ------------------------------------------------------------------------------- __ __ __ __ , __ __ /_/ / /_ /_ /_//_ 16th IEEE REAL-TIME SYSTEMS SYMPOSIUM / \ / __/__/ __/__/ December 4-7, 1995 -- Pisa, Italy ------------------------------------------------------------------------------- Advance Program & Call for Participation IEEE Real-Time Systems Symposium December 4-7, 1995 Palazzo dei Congressi Via Matteotti, 1 Pisa, Italy Sponsored by The IEEE Computer Society Technical Committee on Real-Time Systems IEEE RTSS'95 Home Page http://cs-www.bu.edu/pub/ieee-rts/rtss95 ------------------------------------------------------------------------------- Monday, December 4 ------------------------------------------------------------------------------- Tutorials (at Scuola Superiore Studi Universitari e Perfezionamento Sant'Anna) Tutorial registration: 8:00am - 2:30pm Tutorial 1: 9:00am - 6:00pm (Full day - 6 hours) Title: Real-time Systems: Specification & Verification Instructors: Henk Schepers, Jozef Hooman, Zhiming Liu, Steve Schneider, Kim Larsen, and Wang Yi Tutorial 2: 9:00am - 12:30pm (Half day - 3 hours) Title: Real-Time Communications Instructors: Ken Tindell and Jay Strosnider Tutorial 3: 2:30pm - 6:00pm (Half day - 3 hours) Title: Real-Time POSIX Instructors: Ted Baker, Doug Locke, and Michael Gonzalez Harbour Symposium registration (at Palazzo dei Congressi): 5:00pm - 8:00pm ------------------------------------------------------------------------------- Tuesday, December 5 ------------------------------------------------------------------------------- 8:00am - 5:00pm Registration 9:30 - 9:45am Opening Address and Welcome General Chair: Krithi Ramamritham Program Chairs: Alan Burns and Yann-Hang Lee 9:45 - 10:45am Session 1: Applications Proving Dynamic Properties in an Aerospace Application Simin Nadjm-Tehrani and Jan-Erik Stromberg Modelling a Real Time Control System Based on Distributed Objects Nigel Baker, Wayne Harris, Chris Wallace, Richard McClatchey and Jean-Marie Le Goff 10:45 - 11:15am Coffee break 11:15 - 1:00pm Session 2: Synchronization and OS A Scalable Real-Time Synchronization Protocol for Distributed Systems Injong Rhee and Graham R. Martin Real-Time Computing with Lock-Free Shared Objects James H. Anderson, Srikanth Ramamurthy, and Kevin Jeffay Kernel-Level Threads for Dynamic, Hard Real-Time Environments Marty Humphrey, Gary Wallace, and John A. Stankovic MiThOS -- A Real-Time Micro-Kernel Threads Operating System Frank Mueller, Viresh Rustagi and Ted Baker 1:00 - 2:30pm Lunch 2:30 - 3:45pm Session 3: Formal Methods HyTech: The Next Generation T. Henzinger, P.-H. Ho, and H. Wong-Toi Two Examples of Verification of Multirate Timed Automata with Kronos Conrado Daws and Sergio Yovine Compositional and Symbolic Model-Checking of Real-Time Systems Kim G. Larsen, Paul Pettersson, and Wang Yi 3:45 - 4:15pm Coffee break 4:15 - 5:30pm Session 4: Scheduling I Value vs Deadline Scheduling in Overload Conditions Giorgio Buttazzo, Marco Spuri and Fabrizio Sensini Dual Priority Scheduling Robert Davis and Andy Wellings An Approach To Handling Overloaded Systems That Allow Skips Gilad Koren and Dennis Shasha 8:00pm Welcome party ------------------------------------------------------------------------------- Wednesday, December 6 ------------------------------------------------------------------------------- 8:00am - 5:00pm Registration 9:30 - 10:45am Session 5: Fault Tolerance Enhancing Real-Time Schedules to Tolerate Transient Faults Sunondo Ghosh, Rami Mellhem and Daniel Mosse A Software Fault Injection Tool on Real-Time Mach Scott Dawson, Farnam Jahanian and Todd Mitton Fault-tolerant Real-Time Communication in FDDI-Based Networks Biao Chen, Sanjay Kamat, and Wei Zhao. 10:45 - 11:15am Coffee break 11:15am - 1:00pm Session 6: Distributed Systems Joint Scheduling of Distributed Complex Periodic and Hard Aperiodic Tasks in Statically Scheduled Systems Gerhard Fohler Optimal Combined Task and Message Scheduling in Distributed Real-Time Systems Tarek F. Abdelzaher, and Kang G. Shin Distributed Pinwheel Scheduling with End-to-End Timing Constraints Chih-wen Hsueh, Kwei-Jay Lin, and Nong Fan The Design of Large Real-Time Systems: The Time-Triggered Approach Hermann Kopetz, Martin Braun, Christian Ebner, Andreas Kruger, Dietmar Millinger, Roman Nossal and Anton Schedl 1:00 - 2:30pm Lunch 2:30 - 3:45pm Session 7: Scheduling II Applicability of Simulated Annealing Methods to Real-Time Scheduling and Jitter Control Marco DiNatale & John A. Stankovic Fairness in Periodic Real-Time Scheduling Sanjoy K. Baruah Robust Aperiodic Scheduling Under Dynamic Priority Systems Marco Spuri, Giorgio Buttazzo and Fabrizio Sensini 3:45 - 4:15pm Coffee break 4:15 - 5:30pm Session 8: Communication On Slot Reuse for Isochronous Services in DQDB Networks Ching-Chih Han, Chao-Ju Hou, and Kang G. Shin Dynamic Real-Time Channel Setup and Tear-Down in DQDB Networks Chao-Ju Hou and Kar Shun Tsoi Modeling Bus Scheduling Policies for Real-Time Systems Kevin Kettler and Jay Strosnider 5:30 - 6:30pm IEEE Real-Time Systems TC meeting 8:00pm Gala Dinner ------------------------------------------------------------------------------- Thursday, December 7 ------------------------------------------------------------------------------- 10:00 - 11:15am Session 9: Specification Compiling Modechart Specifications Carlos Puchol, Aloysius K. Mok and Douglas A. Stuart The Specification and Schedulability Analysis of Real-Time Systems using ACSR J. Choi, I. Lee and H. Xie A Graphical Language with Formal Semantics for the Specification and Analysis of Real-Time Systems Hanene Ben-Abdallah, Insup Lee, and Jin-Young Choi 11:15 - 11:45am Coffee break 11:45am - 1:00pm Session 10: Timing Analysis Integrating the Timing Analysis of Pipelining and Instruction Caching Chris Healy, Dave Whalley, and Marion Harmon Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study Yerang Hur, Young Hyun Bae, Sung-Soo Lim, Sung-Kwan Kim, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, and Chong Sang Kim 1:00 - 2:30pm Lunch 2:30 - 3:45pm Sessions 11: Real-Time DB and Window Systems Some Performance Issues for Database Transactions with Firm Deadlines Y. C. Tay Managing Contention and Timing Constraints in a Real-Time Database System Matthew R. Lehr, Young-Kuk Kim, and Sang H. Son ARTIFACT: A Platform for Evaluating Real-Time Window System Designs John Sasinowski and Jay Strosnider ------------------------------------------------------------------------------- Symposium Exhibition ------------------------------------------------------------------------------- An exhibition of hardware and software products for real-time systems will be held in conjunction with the symposium. Any industrial and university groups wishing to participate in the exhibition should contact with Christian Koza at Christian.Koza@aut.alcatel.at. ------------------------------------------------------------------------------- Local Information ------------------------------------------------------------------------------- Conference Site: Palazzo dei Congressi Phone: +39 - 50 - 598.139 Via Matteotti, 1 Phone: +39 - 50 - 598.203 Pisa, Italy Fax: +39 - 50 - 598.112 The City Pisa is a small friendly city in the north of Italy. Apart from its famous Leaning Tower it has a number of other historical attractions and fine restaurants. The Palazzo dei Congressi and all these attractions are within easy walking distance of the hotels listed below. How to reach Pisa There are direct flights to Pisa from London, Paris, Frankfurt, Rome and Milan. The city is also accessible by train from Genoa (2 hours), Rome (3 hours), Milan (4 hours) and Venice (5 hours). Lunch Lunches will be served at the Palazzo dei Congressi and it is included in the registration fee. The price per lunch for accompanying persons is of Lira 40,000. Banking Service A currency exchange office will be located inside of the Palazzo dei Congressi (9:00am - 1:00pm and 2:45pm - 3:45pm). Telephone, fax, and e-mail service During the symposium, participants may receive messages by phone and fax at the Palazzo dei Congressi. Also an E-mail service will be provided. ------------------------------------------------------------------------------- Social Events ------------------------------------------------------------------------------- 1. On Tuesday, December 5th, a welcome party will be offered to the participants. 2. On Wednesday, December 6th, a Gala Dinner will be offered in a typical Tuscan restaurant. ------------------------------------------------------------------------------- Registration ------------------------------------------------------------------------------- Advance registrations should be made by filling the registration form included in the program and mailing it to one of the following: Linda BUSS Route 1, Box 187B, Menomonie, WI 54751 USA OR Ettore RICCIARDI IEI - CNR Via S. Maria, 46 56126 - PISA Italy E-mail registration can be done by sending the registration form to: ricciardi@iei.pi.cnr.it For Credit card payment, please include the name on the credit card, the number of the credit card, the type of the credit card, the expiration date on the credit card, and your signature. Only US or International Bank Checks will be accepted or, alternatively, by an International Bank Transfer order payable to: Ettore RICCIARDI Bank Code Number: 0861 - 5608 - 14002 - 13761 Banca Popolare di Novara - Agency 1 Via San Francesco, 54 56100 - Pisa Italy Please, enclose the check/cheque or a copy of the payment order with the registration form. On site registration fees can be paid by check/cheque, major credit cards, or cash at the Symposium Secretariat. The Secretariat will be open on Monday, December 4th, 1995 from 5:00pm to 8:00pm, and all day during the Symposium. Symposium Registration Fees: --------------------------- Advance (before November 1, 1995) Late (after November 1, 1995) Member: US$ 380 US$ 460 Non-member: US$ 480 US$ 580 Full-time student: US$ 150 US$ 180 Full Day Tutorial Fees: ---------------------- Advance (before November 1, 1995) Late (after November 1, 1995) Member: US$ 170 US$ 210 Non-member: US$ 215 US$ 260 Full-time student: US$ 170 US$ 210 Half Day Tutorial Fees: ---------------------- Advance (before November 1, 1995) Late (after November 1, 1995) Member: US$ 100 US$ 120 Non-member: US$ 120 US$ 140 Full-time student: US$ 100 US$ 120 Notes: ----- 1. Symposium registration includes admission to symposium, a copy of symposium proceedings, lunches, coffee-breaks, Welcome party on Tuesday night, and Gala dinner on Wednesday night. 2. Full-time students are asked to provide a verification of their status, either during registration or at the conference. 3. There are no special full-time student rates for tutorials. 4. Extra ticket for Wednesday's Gala dinner can be purchased at US$ 45/ea. 5. Written requests for refunds must be postmarked no later than November 13, 1995. Refunds are subject to a US$ 50 processing fee. All no-show registration will be billed in full. Registration after 11/13/95 will be accepted on-site only. . . . . . . . . . . . . . . . . . Cut Here . . . . . . . . . . . . . . . . . 1995 IEEE Real-Time Systems Symposium Registration Form First Name:_________________________ Last Name:_____________________________ Title :_____________________________ Position:______________________________ Affiliation:_________________________________________________________________ Address:_____________________________________________________________________ City:_______________________________ State:_________________________________ Country:____________________________ Zip/Postal Code:_______________________ Phone:______________________________ Fax:___________________________________ E-Mail:_____________________________ Payment: Symposium registration fee: Category___________________ $___________ IEEE/ACM Member no:___________________ Tutorial fee: 1. Real-time Systems: Specif. & Verification $___________ 2. Real-Time Communications $___________ 3. Real-Time POSIX $___________ Extra Gala dinner tickets: ($45/ea) $___________ Extra symposium proceedings: ($35/ea) $___________ Hotel reservation deposit: (single or double) $___________ first preference:_____________________ second preference:____________________ third preference:_____________________ Total amount: $___________ . . . . . . . . . . . . . . . . . Cut Here . . . . . . . . . . . . . . . . . ------------------------------------------------------------------------------- Pisa Hotel Information ------------------------------------------------------------------------------- All reservations refer to the period of December 3-8, 1995. Rooms will be available up to November 3, 1995. One night deposit is required for all reservations. All prices are in US dollars and include service and taxes. Approximate conversion rate: $ 1.00 = L 1,600 ------------------------------------------------------------------ price price stars single double ------------------------------------------------------------------ Hotel CAVALIERI ***** 100 120 Piazza della Stazione, 2 Phone: 43.290 Fax: 502.242 ------------------------------------------------------------------ Hotel DUOMO **** 95 130 Via Santa Maria, 94 Phone: 561.894 Fax: 560.418 ------------------------------------------------------------------ Hotel TOURING *** 55 75 Via Puccini, 24 Phone: 46.374 Fax: 502.148 ------------------------------------------------------------------ Hotel TERMINUS & PLAZA *** 50 75 Via Colombo, 45 Phone: 500.303 or 45.200 Fax: 500.303 (to switch) ------------------------------------------------------------------ Hotel LA PACE *** 45 60 Viale Gramsci, Gall. B Phone: 48.863 or 29.351 Fax: 502.266 ------------------------------------------------------------------ Other Hotels without reservation for RTSS price price stars single double ------------------------------------------------------------------ Hotel D'AZEGLIO **** 90 120 Piazza Vittorio Emanuele, 18 Phone: 500.310 Fax: 28.017 ------------------------------------------------------------------ Hotel VILLA KINZICA *** 65 85 Piazza Arcivescovado, 2 Phone: 560.419 Fax: 551.204 ------------------------------------------------------------------ Hotel MINERVA *** 60 80 Piazza Toniolo, 20 Phone: 501.018 Fax: 551.204 ------------------------------------------------------------------ **** IMPORTANT: Please, mention the RTSS when reserving the hotel room. ------------------------------------------------------------------------------- LOCAL INFORMATION SERVICE ------------------------------------------------------------------------------- For any information about local arrangements, please send E-mail to: Giorgio Buttazzo: giorgio@sssup1.sssup.it Ettore Ricciardi: ricciardi@iei.pi.cnr.it ------------------------------------------------------------------------------- Conference Committee ------------------------------------------------------------------------------- General Chair Krithi Ramamritham Program Chairs Alan Burns and Yann-Hang Lee Treasurers Walt Heimerdinger and Ettore Ricciardi Publicity Chairs Azer Bestavros and Ken Tindell Industrial Chairs Michelle Hugue and Christian Koza Local Arrangements Giorgio Buttazzo and Ettore Ricciardi Ex-Officio Al Mok ----------------------- Program Committee ----------------------- | | | Ted Baker Giorgio Buttazzo Juan A. DeLaPuente | | Richard Gerber Nicholas Halbwachs Hans Hansson | | Connie Heitmeyer Jozef Hooman Farnam Jahanian | | Kevin Jeffay Theodore Johnson Mathai Joseph | | Dilip Kandlur Hermann Kopetz C. Mani Krishna | | Kwei-Jay Lin Fabio Panzieri David Powell | | Lui Sha Parmesh Ramanathan Hans Rischel | | Mike Rodd Fred Schneider Dennis Shasha | | Kang Shin Sang Son Jack Stankovic | | Jay Strosnider Reino Suonio Sandra Thuel | | Kenji Toda Paulo Verissimo Andy Wellings | | Wei Zhao | ----------------------------------------------------------------- ------------------------------------------------------------------------------- For more information, including abstracts of technical papers please check The IEEE RTSS'95 Home Page at URL http://cs-www.bu.edu/pub/ieee-rts/rtss95 ------------------------------------------------------------------------------- Subject: RTSS'95: Abstracts of Technical Presentations Session 1: Applications Proving Dynamic Properties in an Aerospace Application Simin Nadjm-Tehrani and Jan-Erik Stromberg Link"oping University, Sweden In this paper we give an exposition to an ongoing research effort in cooperation with aerospace industries in Sweden. We report on an application of formal verification techniques on a landing gear system. This system consists of actuating hydromechanic and electromechanic hardware, and of controlling software components. We emphasize the need for modelling techniques and languages covering the whole spectrum from informal engineering documents, to hybrid mathematical models. In this modelling process we give as much weight to the physical environment as to the controlling software. We show the application of two verification methods for proving safety and timeliness properties of the closed loop system; first, using the proof system of extended duration calculus, and second by symbolic model checking. Modelling a Real Time Control System Based on Distributed Objects Nigel Baker, Wayne Harris, Chris Wallace, Richard McClatchey and Jean-Marie Le Goff University of the West of England, Frenchay Campus The CERN Research and Development project (RD-38), named CICERO [1], aims to identify and design the main building blocks of a generic control information system based on distributed objects. The project is producing an integrating framework (named Cortex [2]) into which user real-time control objects will ultimately be plugged (and played) and a control information system to support its configuration and management. Development of Cortex is following the ESA PSS-05-02 software engineerin standards [3]. Cortex is providing an environment which allows real-time control systems to share information, control and analysis functions; which presents an uniform human interface; which permits upgrades and additions without code modification; and which is sufficiently generic to allow its use both by existing or future control systems at CERN and by industrial real-time control systems. It provides both high level data access, abstracting objects to a level appropriate for online control and low level data access to allow views of experimenta sub-components for detailed real-time control. Additionally, the Cortex system shall enable developers to grow their control systems from a lab-based test system to the complete experimental system and is therefore both scalable and flexible to change. Technical solutions are being identified in CICERO which could later be the major components of a basic turnkey control system for future medium to large scale HEP experiments and accelerators as well as for industrial real-time control systems. This paper outlines the modelling concepts behind Cortex. ------------------------------------------------------------------------------- Session 2: Synchronization and OS A Scalable Real-Time Synchronization Protocol for Distributed Systems Injong Rhee and Graham R. Martin University of Warwick, UK A distributed protocol is proposed for the synchronization of real-time tasks that have variable resource requirements. The protocol is simple to implement and is intended for large-scale distributed or parallel systems in which processes communicate by message passing. Critical sections, even when nested, may be executed on any processor. Thus, given an adequate number of processors, the execution of critical sections can be completely distributed. More significantly, since the protocol enables the distributed allocation of critical sections, the benefits of various allocations can be analyzed and the system optimized to provide minimal blocking. This has important application in global optimization techniques for allocating large numbers of hard real-time tasks in multiprocessor systems. Real-Time Computing with Lock-Free Shared Objects James H. Anderson, Srikanth Ramamurthy, and Kevin Jeffay University of North Carolina This paper considers the use of lock-free shared objects within hard real-time systems. As the name suggests, lock-free shared objects are distinguished by the fact that they are not locked. As such, they do not give rise to priority inversions, a key advantage over conventional, lock-based object-sharing approaches. Despite this advantage, it is not immediately apparent that lock-free shared objects can be employed if tasks must adhere to strict timing constraints. In particular, lock-free object implementations permit concurrent operations to interfere with each other, and repeated interferences can cause a given operation to take an arbitrarily long time to complete. The main contribution of this paper is to show that such interferences can be bounded by judicious scheduling. This work pertains to periodic, hard real-time tasks that share lock-free objects on a uniprocessor. In the first part of the paper, scheduling conditions are derived for such tasks, for both static and dynamic priority schemes. Based on these conditions, it is formally shown that lock-free object-sharing approaches can be expected to incur much less overhead than approaches based on wait-free objects or lock-based schemes. In the last part of the paper, this conclusion is validated experimentally through work involving a real-time desktop videoconferencing system. Kernel-Level Threads for Dynamic, Hard Real-Time Environments Marty Humphrey, Gary Wallace, and John A. Stankovic University of Massachusetts The design of a kernel-level thread package for dynamic, hard real-time environments is presented. A highly integrated design is used to ensure predictability. A system description language and real-time programming language are used to specify key properties of threads and thread groups. For a thread, this includes whether or not the thread spawns other threads at run-time, the type of performance guarantee the thread requires, how the thread interacts with other threads, and what processors the thread may execute on. A predictable kernel uses this information along with on-line dynamic guarantees to ensure predictable execution of threads. The first phase of the thread package has been implemented and performance measurements have indicated a 66% improvement in context switching costs. MiThOS -- A Real-Time Micro-Kernel Threads Operating System Frank Mueller*, Viresh Rustagi** and Ted Baker*** * Humboldt-Universitat zu Berlin ** Microtec Research Inc. *** Florida State University MiThOS (Micro-kernel Threads Operating System) is an experimental operating system for embedded systems. The system kernel is a first implementation of the POSIX ``Minimal Real-Time System Profile''. It is based on prior work of a library implementation of Pthreads (POSIX threads). The system is fully preemptive. It supports multi-threading within a single process environment with shared kernel and user space, {\em i.e.} real-time tasks are mapped onto POSIX threads. It exhibits remarkable timing predictability intended for hard real-time requirements. This is achieved by a careful design of only few device drivers. The system has been implemented and tested on the SPARC VME architecture. The system includes a fast context switching algorithm for the SPARC which outperforms the context switch under SunOS and matches the performance under Solaris. It supports selective enabling and disabling of hardware components (MMU, caches, etc.) since its sources are available. Furthermore, an implementation-defined extension of POSIX threads for deadline scheduling is presented. Overall, the system exhibits slightly faster performance than SunOS 4.x and is considerably more predictable in its timing behavior. Applications of the kernel range from evaluating the overhead of new language features in Ada 95 and its runtime system, verifying static timing predictions on a bare machine, to providing the operating system for small embedded system that require a high timing predictability. ---------------------------------------------------------------------------- Session 3: Formal Methors HyTech: The Next Generation T. Henzinger, P.-H. Ho, and H. Wong-Toi Cornell University We describe a new implementation of \hytech\,---\,a symbolic model-checker for hybrid systems. Given a parametric description of an embedded system as a collection of communicating automata, \hytech\ automatically computes the conditions on the parameters under which the system satisfies its safety and timing requirements. While the original \hytech\ prototype was based on the symbolic algebra tool Mathematica, the new implementation is written in C++ and builds on geometric algorithms instead of formula manipulation. The new \hytech\ offers a cleaner and more expressive input language, greater portability, and dramatically superior performance (typically two to three orders of magnitude). We illustrate the effectiveness of the new implementation by applying \hytech\ to the automatic parametric analysis of the generic railroad crossing (GRC) benchmark problem~\cite{HJL93} and to an active structure control algorithm~\cite{ECB94}. Two Examples of Verification of Multirate Timed Automata with Kronos Conrado Daws and Sergio Yovine VERIMAG, France Multirate timed automata are an extension of timed automata where each clock has its own speed varying between a lower and an upper bound that may change from one control location to another. This formalism is well-suited for specifying hybrid systems where the dynamics of the continuous variables are defined or can be approximated by giving the minimal and maximal rate of change. To avoid the difficulties inherent to the verification of multirate timed automata, we follow the approach suggested in (1). This approach consists in first transforming the multirate timed automata into timed automata and then applying the symbolic techniques implemented in Kronos. We show the practical interest of this approach analyzing two examples recently proposed in the literature and considered to be realistic case studies: the manufacturing plant of (2) and the Philips audio control protocol (3). (1) "Using abstractions for the verification of linear hybrid systems", A. Olivero and J. Sifakis and S. Yovine, LNCS 818, p. 81-94. (2) "Verification of hybrid systems using abstractions" A. Puri and P. Varaiya, Hybrid Systems Workshop, Cornell University, October 1994. (3) "Verification of an audio control protocol" D. Bosscher and I. Polak and F. Vaandrager, LNCS 863, p. 170-192. Compositional and Symbolic Model-Checking of Real-Time Systems Kim G. Larsen, Paul Pettersson, and Wang Yi Uppsala University, Sweden Efficient automatic model--checking algorithms for real-time systems have been obtained in recent years based on the state--region graph technique of Alur, Courcoubetis and Dill. However, these algorithms are faced with two potential types of explosion arising from parallel composition: explosion in the space of control nodes, and explosion in the region space over clock-variables. In this paper we attack these explosion problems by developing and combining compositional and symbolic model--checking techniques. The presented techniques provide the foundation for a new automatic verification tool Uppaal. Experimental results show that Uppaal is not only substantially faster than other real-time verification tools but also able to handle much larger systems. ----------------------------------------------------------------------------- Session 4: Scheduling I Value vs Deadline Scheduling in Overload Conditions Giorgio Buttazzo, Marco Spuri and Fabrizio Sensini Scuola Superiore S. Ann, Italya In this paper we present a comparative study among scheduling algorithms which use different priority assignments and different guarantee mechanisms to improve the performance of a real-time system during overload conditions. In order to increase the information available to the system for enhancing the quality of service, we assume that tasks are characterized not only by a deadline, but also by an importance value. The performance of the scheduling algorithm is then evaluated by computing the cumulative value gained on a task set, i.e. the sum of the values of those tasks that completed by their deadline. The purpose of this simulation study was twofold. Firstly, we wanted to discover which priority assignment is able to achieve the best performance in overload conditions. Secondly, we were interested in understanding how the pessimistic assumptions made in the guarantee test affect the performance of the scheduling algorithms, and how much a reclaiming mechanism can compensate this degradation. To answer these questions, in our study we have considered four classical priority assignments, that we have tested using three different guarantee mechanisms, thus comparing a total number of twelve scheduling algorithms. The results are interesting and provide a useful reference for building robust real-time systems for practical control applications. Dual Priority Scheduling Robert Davis and Andy Wellings University of York In this paper, we present a new strategy for scheduling tasks with soft deadlines in real-time systems containing periodic, sporadic and adaptive tasks with hard deadlines. In such systems, much of the spare capacity present is due to sporadic and adaptive tasks not arriving at their maximum rate. Offline methods of identifying spare capacity such as the Deferrable Server or Priority Exchange Algorithm are unable to make this spare capacity available as anything other than a background service opportunity for soft tasks. Further, more recent methods such as dynamic Slack Stealing require computationally expensive re-evaluation of the available slack in order to reclaim such spare capacity. By comparison, the Dual Priority approach presented in this paper provides an efficient and effective means of scheduling soft task in this case. Skip-Over: Algorithms and Complexity for Overloaded Systems That Allow Skips Gilad Koren and Dennis Shasha Bar-Ilan U., ISRAEL Courant Institute, NYU In applications ranging from video reception to telecommunications and packet communication to aircraft control, tasks enter periodically and have fixed response time constraints, but missing a deadline is acceptable, provided most deadlines are met. We call such tasks ``occasionally skippable.'' We look at the problem of uniprocessor scheduling of occasionally skippable periodic tasks. We show that making optimal use of skips is NP-hard. We then look at algorithms for scheduling such systems. -------------------------------------------------------------------------- Session 5: Fault Tolerance Enhancing Real-Time Schedules to Tolerate Transient Faults Sunondo Ghosh, Rami Mellhem and Daniel Mosse University of Pittsburgh We present a scheme that can be used to guarantee that the execution of real-time tasks can tolerate transient and intermittent faults. The scheme is based on reserving sufficient slack in a schedule such that a task can be re-executed before its deadline without compromising the guarantees given to other tasks. Instead of reducing the schedulability by 50\% by simply leaving enough time in the schedule for each task to re-execute, we take the Mean Time To Failure (MTTF) into account. We leave only enough slack in the schedule to guarantee fault tolerance if at most one fault occurs within a time interval, e.g., a factor of the MTTF. This results in increased schedulability and a very low percentage of deadline misses even if no restriction is placed on the fault separation. We show that this methodology can be applied to any queue-based scheduling technique for real-time tasks, and provide simulation results for some common scheduling policies. We also provide two algorithms to solve the problem of adding fault tolerance to a queue of real-time tasks. The first is a dynamic programming solution to find the optimal placement of backups in the queue which maximizes schedulability while providing fault tolerance. The second is a heuristic which closely approximates the optimal. We also present a comparison between the two algorithms, and a detailed evaluation of one of the two algorithms. A Software Fault Injection Tool on Real-Time Mach Scott Dawson, Farnam Jahanian and Todd Mitton University of Michigan Ensuring that a distributed real-time system with strict dependability constraints meets its prescribed specification is a growing challenge that confronts software developers and system engineers. This paper reports on a software fault injection tool, called sockPFI, for testing the fault tolerance and timing behavior of distributed real-time applications. The sockPFI, developed on Real-Time Mach, can be used to test socket-based distributed real-time applications on this platform without modifying the source code of the target protocol. The sockPFI tool is based on the concept of Script-Driven Probing and Fault Injection \cite{dawson:94b}. It is explicitly designed to address some of the intrusiveness associated with fault injection of distributed systems, and in particular, with real-time protocols. The paper describes the design and implementation of sockPFI on Real Time Mach. This paper also describes a demonstration of the tool on a real-time primary-backup replication protocol. Fault-tolerant Real-Time Communication in FDDI-Based Networks Biao Chen, Sanjay Kamat, and Wei Zhao Texas A&M University In mission-critical systems, messages have hard real-time constraints as well as certain fault-tolerance requirements. Often some critical messages may have to be transmitted by their deadlines even when the system detects certain faults at run-time. FDDI-Based Reconfigurable Networks have an architecture that is suitable for mission-critical systems. This architecture uses multiple FDDI networks to connect hosts and provides for automatic reconfiguration to maintain high network bandwidth in spite of faults. Extensive studies have been carried out on the design of reconfiguration algorithms for this architecture. An important open problem is how resources in such networks should be managed in order to guarantee that the fault-tolerant real-time requirements of messages are met. This paper presents an efficient and practical solution to this problem. Our solution consists of off-line and on-line components. On-line management deals with run-time manipulation of messages and network resources. A message grouping approach simplifies on-line management. Off-line management deals with organizing messages into groups, allocating bandwidth to messages and verifying that all the fault-tolerant real-time requirements are met. Three approaches are investigated: spatial redundancy approach that relies on sending multiple copies of a message, temporal redundancy approach that allows for migration of a message from faulty to nonfaulty rings, and an integrated approach that uses a combination of both. It is shown that the integrated approach has the best performance. Our solution is compatible with the FDDI and SAFENET standards. ------------------------------------------------------------------------------ Session 6: Distributed Systems Joint Scheduling of Distributed Complex Periodic and Hard Aperiodic Tasks in Statically Scheduled Systems Gerhard Fohler University of Massachusetts In this paper we present algorithms for the joint scheduling of periodic and aperiodic tasks in statically scheduled distributed real-time systems. Periodic tasks are precedence constrained, distributed, and communicating over the nodes of the systems. Both soft and hard aperiodic tasks are handled. After a static schedule has been created in a first step, the algorithms determine the amount and distribution of unused resources and leeway in it. These are then used to incorporate aperiodic tasks into the schedule by shifting the periodic tasks' execution, without violating their feasibility. Run-time mechanisms are simple and require only little memory. Processors and communication nodes can be utilized fully. The algorithm performs an optimal online guarantee algorithm for hard aperiodic tasks of O(N). Optimal Combined Task and Message Scheduling in Distributed Real-Time Systems Tarek F. Abdelzaher, and Kang G. Shin University of Michigan In this paper we present an optimal algorithm for {\em combined\/} task and message scheduling in distributed hard real-time systems. The algorithm finds an optimal schedule for a set of communicating tasks with known arrival times, precedence constraints, and resource requirements in conjunction with the assignment and scheduling of intertask messages over communication links. Processing nodes are assumed to be joined by an arbitrary topology point-to-point interconnection network. The algorithm employs a branch-and-bound (B\&B) technique to find an optimal solution for the combined task and message scheduling problem. The solution is ``optimal'' in the sense of minimizing maximum task lateness, defined as the difference between task completion time and deadline. It has the property of generating a complete schedule at each vertex in the search tree, and can be made to produce the first encountered feasible solution if needed. A robotics application is used to illustrate the potential of the algorithm. Results of an extensive simulation study analyzing its performance are reported. The algorithm is shown to find the optimal solution near the root of the search for a large range of systems. The algorithm also scales well with respect to system size, and degree of interaction among system tasks. It has good performance for workloads spanning a large range of CPU utilization and degrees of application concurrency. Distributed Pinwheel Scheduling with End-to-End Timing Constraints Chih-wen Hsueh, Kwei-Jay Lin, and Nong Fan University of California, Irvine Scheduling algorithms for allocating resources and scheduling tasks are important to the success of many real-time systems with end-to-end performance requirements. In this paper, an end-to-end scheduling model based on the pinwheel scheduling algorithms is presented for distributed real-time systems. We discuss how tasks on different nodes may be transformed to have harmonic periods. We also present algorithms to adjust the phases between schedules on neightboring node so that the overall end-to-end delay is reduced. Using the pinwheel approach, schedules on different nodes are closely synchronized and more static. However, the payoff is the more predictable performance with a shorter end-to-end delay. We believe that our work in this paper provides a practical approach to the design of many static real-time systems. The Design of Large Real-Time Systems: The Time-Triggered Approach Hermann Kopetz, Martin Braun, Christian Ebner, Andreas Kruger, Dietmar Millinger, Roman Nossal and Anton Schedl Technische Universit"at Wien, Austria ------------------------------------------------------------------------------ Session 7: Scheduling II Applicability of Simulated Annealing Methods to Real-Time Scheduling and Jitter Control Marco DiNatale & John A. Stankovic University of Massachusetts This paper presents a non-conventional scheduling approach for distributed static systems where tasks are periodic and have arbitrary deadlines, precedence, and exclusion constraints. The solution presented in this work not only creates feasible schedules, but also minimizes jitter for periodic tasks. The problem of scheduling real-time tasks with minimum jitter is particularly important in many control applications, nevertheless, it has been rarely studied in the scientific literature. We present a general framework consisting of an abstract architecture model and a general programming model. We show how to design a surprisingly simple and flexible scheduling method based on simulated annealing and present some experimental results. Fairness in Periodic Real-Time Scheduling Sanjoy K. Baruah New Jersey Institute of Technology The issue of temporal fairness in periodic real-time scheduling is considered. It is argued that such fairness is often a desirable characteristic in real-time schedules. A quantitative measure of temporal fairness --- pfairness --- is described. The Weight-Monotonic scheduling algorithm, a static priority scheduling algorithm for generating pfair schedules, is presented and proven correct. A feasibility test is presented which, if satisfied by a periodic task system, ensures that the Weight-Monotonic scheduling algorithm will schedule the system in a pfair manner. Robust Aperiodic Scheduling Under Dynamic Priority Systems Marco Spuri, Giorgio Buttazzo and Fabrizio Sensini Scuola Superiore S. Ann, Italya When hard periodic and firm aperiodic tasks are jointly scheduled in the same system, the processor workload can vary according to the arrival times of aperiodic requests. In order to guarantee the schedulability of the periodic task set, in overload conditions some aperiodic tasks must be rejected. In this paper we propose a technique that, in overload conditions, adds robustness to the joint scheduling of periodic and aperiodic tasks in systems with dynamic priorities. Our technique is based on an aperiodic server, called Total Bandwidth server, already proven effective in a previous work. Here the algorithm is first extended to efficiently handle firm aperiodic tasks and then integrated with a robust guarantee mechanism that allows to achieve graceful degradation in case of transient overloads. Extensive simulations show that the proposed new algorithm is effective in all workload conditions. ------------------------------------------------------------------------------- Session 8: Communication On Slot Reuse for Isochronous Services in DQDB Networks Ching-Chih Han*, Chao-Ju Hou** and Kang G. Shin* * University of Michigan ** Univerity of Wisconsin-Madison The Distributed Queue Dual Bus (DQDB) protocol has been jointly adopted by IEEE and ANSI as a standard (IEEE802.6) for metropolitan area networks (MANs). As such, DQDB has become the focus of many studies. In addition to the numerous studies performed on the queueing performance [3,6,18] and the fairness issue [2, 12, 13, 26], the issue of how to effectively provide various services in DQDB networks has also received increasing attention [14, 24]. In [14], we devised a slot allocation scheme for allocating pre-arbitrated (PA) slots to isochronous message streams in DQDB networks. We laid a formal basis for guaranteeing the timely delivery of isochronous (real-time) messages with hard deadlines. In this paper, we extend our work in [14] and address on how to improve the performance of the slot allocation scheme (in terms of bandwidth utilization) by using the concept of slot reuse. We devise several slot reuse schemes to assign spatially non-intersecting message streams to share the same virtual connections (i.e., the same set of PA slots identified by the VCI numbers). The slot reuse schemes proposed in this paper are simple, can be easily incorporated into the slot allocation scheme proposed in [14], and requires only a minor change in the current DQDB standards. Dynamic Real-Time Channel Setup and Tear-Down in DQDB Networks Chao-Ju Hou and Kar Shun Tsoi Univerity of Wisconsin-Madison The Distributed Queue Dual Bus (DQDB) protocol has been jointly adopted by IEEE and ANSI as a standard (IEEE802.6) for metropolitan area networks (MAN). As such, how to provide various services in the DQDB protocol has attracted increasing attention. In particular, how to guarantee the timely delivery of isochronous (real-time) messages with hard deadline constraints is one of the open issues yet to be solved. In [12], we laid a formal basis for allocating pre-arbitrated (PA) slots to isochronous message streams in DQDB networks and devised a slot allocation scheme to statically establish a set of isochronous message streams at system initialization. In this paper, we complement our work in [12] and propose a dynamic channel setup and tear-down scheme for DQDB networks. During system operation, we artificially treat the QA slots as slots assigned to a pseudo channel, called an empty channel. In response to a call setup request, the proposed scheme first verifies whether or not the new channel can be feasibly established without jeopardizing the timing constraints of existing channels by checking a certain schedulability condition. If the schedulability condition is satisfied, the channel establishment procedures are invoked to set up this new channel by using the slots originally assigned to the empty channel. In response to a call clear request, the channel termination procedures are invoked to free the slots originally allocated to the terminated channel by marking them as slots allocated to an empty channel. The channel termination procedures then merge this newly freed channel and the existing empty channel into one. The resulting channel establishment and termination procedures are simple, can be easily implemented in DQDB networks, and do not require any changes in the current DQDB standards. Modeling Bus Scheduling Policies for Real-Time Systems Kevin Kettler and Jay Strosnider Carnegie Mellon University This paper introduces formal scheduling models for several common system bus architectures found in PC and workstation systems. The scheduling models are abstractions which enable one to reason about the timing correctness of a bus transferring real-time traffic. The models provide a quantitative means to explore the design space of bus implementations. This paper provides a simple, unambiguous approach for the creation of scheduling models which can be used efficiently by a bus designer or system user to improve real-time bus performance without the need for detailed real-time scheduling knowledge. The step by step process of model development is presented. The utility of the scheduling models is demonstrated by analyzing several common system buses. ------------------------------------------------------------------------------- Session 9: Specification Compiling Modechart Specifications Carlos Puchol, Aloysius K. Mok and Douglas A. Stuart University of Texas at Austin The Modechart specification language is a formalism for the specification of real-time systems. A toolset for specification, analysis and simulation for Modechart specifications exists for supporting the design and construction of real-time systems. This paper introduces a new tool in the the toolset: a compiler for a class of Modechart specifications, namely, that of deterministic system specifications, extended by a subclass of the non-deterministic system specifications. The object code that the compiler generates is in Esterel, a member of the synchronous family of programming languages for real-time systems. We discuss a broad approach to the implementation of timing specifications, providing a range of implementation options, from the basic time step unrolling of states in Esterel, to the use of system timers. The compiler presented herein allows the specifier to obtain a correct implementation of a modechart program, including timing constraints. The Specification and Schedulability Analysis of Real-Time Systems using ACSR J. Choi, I. Lee and H. Xie University of Pennsylvania To engineer reliable real-time systems, it is desirable to detect timing anomalies early in the development process. However, there is little work addressing the problem of accurately predicting timing properties of real-time systems before implementations are developed. This paper describes an approach to the specification and schedulability analysis of real-time systems based on the timed process algebra ACSR-VP, which is an extension of ACSR with value-passing communication and dynamic priorities. Combined with the existing features of ACSR for representing time, synchronization and resource requirements, ACSR-VP is capable of specifying a variety of real-time systems with different scheduling disciplines in a modular fashion. Moreover, we can perform schedulability analysis on real-time systems specified in ACSR-VP automatically by checking for a certain bisimulation relation. A Graphical Language with Formal Semantics for the Specification and Analysis of Real-Time Systems Hanene Ben-Abdallah, Insup Lee, and Jin-Young Choi University of Pennsylvania Graphical Communicating Shared Resources, GCSR, is a formal language for the specification and analysis of real-time systems including their functional and resource requirements. GCSR allows a modular and hierarchical, thus, scalable specification of a real-time system. GCSR supports notions of communication through events, interrupt, concurrency, and time to describe the functional requirements of a real-time system. In addition, GCSR allows the explicit representation of resources and priorities to arbitrate resource contention in a natural way that produces easy to understand and modify specifications. The semantics of GCSR is the Algebra of Communicating Shared Resources, a timed process algebra with operational semantics. The process algebra ACSR provides behavioral equivalence relations which can be used to verify the correctness of one GCSR specification with respect to the other. ------------------------------------------------------------------------------ Session 10: Timing Analysis Integrating the Timing Analysis of Pipelining and Instruction Caching Chris Healy*, Dave Whalley* and Marion Harmon** * Florida State University ** Florida A&M University Recently designed machines contain pipelines and caches. While both features provide significant performance advantages, they also pose problems for predicting execution time of code segments in real-time systems. Pipeline hazards may result in multicycle delays. Instruction or data memory references may not be found in cache and these misses typically require several cycles to resolve. Whether an instruction will stall due to a pipeline hazard or a cache miss depends on the dynamic sequence of previous instructions executed and memory references performed. Furthermore, these penalties are not independent since delays due to pipeline stalls and cache miss penalties may overlap. This paper describes an approach for bounding the worst-case performance of large code segments on machines that exploit both pipelining and instruction caching. First, a method is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. Next, these categorizations are used in the pipeline analysis of sequences of instructions representing paths within the program. A timing analyzer uses the pipeline path analysis to estimate the worst-case execution performance of each loop and function in the program. Finally, a graphical user interface is invoked that allows a user to request timing predictions on portions of the program. Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe Princeton University Real-time systems are characterized by the presence of timing constraints in which a task must be completed within a specific amount of time interval. This paper examines the problem of determining the bound on the worst case execution time (WCET) of a given program on a given processor. There are two important issues in solving this problem: (i) program path analysis, which determines what sequence of instructions will be executed in the worst case, and (ii) microarchitectural modeling, which models the hardware system and determines the WCET of a known sequence of instructions. To obtain a tight estimate on the bound, both of these issues must be addressed accurately and efficiently. The later is becoming difficult to model for modern processors due to the presence of pipelined instruction execution units and cached memory systems. All existing methods that the authors know of focus only on either one of above issues. They also adopt the path oriented approach to solve the problem, in which an exhaustive search on all feasible program paths is required. These limit the accuracy of the estimated bound and the size of the program that can be analyzed. We present a more effective solution for solving this problem. It addresses both issues and uses an integer linear programming formulation to solve the problem. Explicit program path enumeration is not required. This solution is implemented in the program cinderella, which currently targets the Intel i960KB processor. Some experimental results are presented here. Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study Yerang Hur, Young Hyun Bae, Sung-Soo Lim, Sung-Kwan Kim, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, and Chong Sang Kim Seoul National University This paper presents a case study of worst case timing analysis for a RISC processor. The target machine consists of the R3000 CPU and R3010 FPA (Floating Point Accelerator). This target machine is typical of a RISC system with pipelined execution units and cache memories. Our methodology is an extension of the existing timing schema. The extended timing schema provides means to reason about the execution time variation of a program construct by surrounding program constructs due to pipelined execution and cache memories of RISC processors. The main focus of this paper is on explaining the necessary steps for performing timing analysis of a given target machine within the extended timing schema framework. This paper also gives results from experiments using a timing tool for the target machine built based on the extended timing schema approach. ----------------------------------------------------------------------------- Sessions 11: Real-Time DB and Window Systems Some Performance Issues for Database Transactions with Firm Deadlines Y. C. Tay National University of Singapore We present a performance model for transactions with firm deadlines running on a database system that uses locking, but without priority scheduling. Such a system may be a legacy, or bought off-the-shelf. Excluding priority scheduling is also a way of determining how resource and data contention affect deadline misses. The model is used to (1) define workload --- a number that helps the evaluation of a system design by predicting the stress on it; (2) show that performance is proportional to the cube of transaction length, so it is crucial that transactions request a minimal number of locks; (3) examine how deadlines should vary if transaction length increases, thus demonstrating the crucial role of resource contention; and (4) consider the issue of fairness and show that execution times and multiprogramming levels can cause a bias only though priority scheduling. We also offer an interpretation of ``missed deadlines must be rare'' in terms of abort cost. Managing Contention and Timing Constraints in a Real-Time Database System Matthew R. Lehr, Young-Kuk Kim, and Sang H. Son University of Virginia Previous work in real-time database management systems (RT-DBMS) has primarily focused on simulation. This paper discusses how current real-time technology has been applied to architect an actual RT-DBMS on a real-time microkernel operating system. A real RT-DBMS must confront many practical issues which simulations typically ignore: race conditions, concurrency, and asynchrony. The challenge of constructing a RT-DBMS is divided into three basic problems: dealing with resource contention, dealing with data contention, and enforcing timing constraints. In this paper, we present our approaches to each problem. ARTIFACT: A Platform for Evaluating Real-Time Window System Designs John Sasinowski and Jay Strosnider Carnegie Mellon University Multimedia and advanced real-time systems integrate a variety of applications and media types in one environment, many of which have timing properties which are not supported by current window systems running in multitasking environments. This paper discusses several key aspects to designing window systems which support continuous media and other real-time applications. These design considerations were used to construct ARTIFACT, a window system designed to investigate issues in building real-time window systems. Several of the behaviors of a partial implementation of ARTIFACT are described, along with preliminary scheduling models and avenues for further research. ***************************************************************************** Postmarked Wed Oct 11 11:24:26 1995 From: best@cs.bu.edu (Azer Bestavros) Subject: RTDB'96: Call for papers Content-Length: 5610 ------------------------------------------------------------------------------ First International Workshop on Real-Time Databases: Issues and Applications March 7-8, 1996 Newport Beach, California CALL FOR PAPERS ------------------------------------------------------------------------------ For more information Check the Workshop's Home Page at the URL below http://www.eng.uci.edu/ece/rtdb/cfp.html ------------------------------------------------------------------------------ Objectives ---------- The workshop has several goals: - to investigate advances in real-time database systems - to promote interaction among real-time database researchers & practitioners - to evaluate the maturity and directions of real-time database technology Workshop attendees will discuss the research issues and applications of real-time database systems and explore novel ideas. Papers describing new ideas, promising approaches, experiences with practical and research systems, and work in progress are considered particularly appropriate. Topics of the workshop include: - Database support for multimedia applications - Real-time databases for WWW servers and applications - Object-oriented paradigms for real-time databases - Advanced data and transaction models - Advanced database architectures for parallel and distributed systems - Requirement specifications and design tools - Interactions with operating systems and programming environments - Real-time scheduling and transaction management - Integration with active, dependable, and secure database features - Applications of real-time database systems - Experiments and practices Submission Guidelines --------------------- Prospective attendees should send an electronic version (postscript file) of their position paper (less than 5 single-spaced pages) by December 1, 1995 to son@virginia.edu. Hard copies are also acceptable and can be mailed to (6 copies): Prof. Sang H. Son Department of Computer Science School of Engineering and Applied Science University of Virginia Charlottesville, VA 22903 USA Email: son@virginia.edu Office: Olsson Hall 218 Phone: (804) 982-2205 Fax: (804) 982-2214 Position papers should focus on insights and lessons gained from recent research and practical experience in real-time database systems and applications. Complete details regarding the workshop will be sent to authors by February 1, 1996. The proceedings of the workshop will be distributed in the workshop and also made available on the web. Selected papers from the workshop will be published as an edited book after the workshop. Important Dates --------------- December 1, 1995 -- Deadline for position paper submissions February 1, 1996 -- Notification of acceptance February 20, 1996 -- Final paper due March 7-8, 1996 -- Workshop Industrial Track and Exhibits ----------------------------- There will be a concurrent industrial track with the exhibit area that allows vendors and users of commercial products the opportunity to discuss their products and experiences. The Industrial Track consists of original technical papers authored and presented by authors from various companies. Possible topics of the track include (but not limited to) descriptions, comparisons, or evaluations of the design, implementation, or performance of some commercial systems. Commercial Exhibits allow vendors to display their products in an informal "walk-up and talk" setting. Companies are encouraged to participate in both of these events. For more details, please contact the program co-chair: Prof. Kwei-Jay Lin Dept of Electrical & Computer Engineering University of California, Irvine Irvine, CA 92717 Phone: (714)824-7839 Fax: (714)824-2321 Email: klin@uci.edu Organizing Committee -------------------- General Chair Jane W.S. Liu , University of Illinois at Urbana-Champaign Program Co-Chairs Sang H. Son, University of Virginia Kwei-Jay Lin, University of California, Irvine Finance Chair Sharad Mehrotra, University of Illinois at Urbana-Champaign Publicity Chair Azer Bestavros, Boston University Local Arrangement Ching-Shan Peng, University of California, Irvine Program Committee Sten Andler Univ. Skoevde, Sweden Alex Buchmann T.U. Darmstadt, Germany Alan Burns Univ. York, UK Jen-Yao Chung IBM Philip Hwang Defense Mapping Agency Kevin Jeffay Univ. of North Carolina Young-Kuk Kim SINTEF, Norway Tei-Wei Kuo National Chung Cheng Univ., Taiwan Kam-yiu Lam City Univ. of Hong Kong Al Mok University of Texas, Austin Gultekin Ozsoyoglu Case Western Reserve University Calton Pu Oregon Graduate Inst. Raj Rajkumar Carnegie Mellon University Krithi Ramamritham University of Massachusetts Kang Shin University of Michigan Bhavani Thurasingham Mitre Corp. Ozgur Ulusoy Bilkent U., Turkey Victor Wolfe Univ. Rhode Island Wei Zhao Texas A&M University ------------------------------------------------------------------------------ Message 2; Postmarked Thu Oct 12 10:35:29 1995 From: lwelch%dorado@relay.nswc.navy.mil (Lonnie Welch) Subject: OORTS'96 Program Content-Length: 10874 ------------------------------------------------------------------------------- FINAL PROGRAM WORKSHOP ON OBJECT-ORIENTED REAL-TIME SYSTEMS Friday, Oct. 27, 1995 San Antonio, Texas, USA (In conjunction with the 7th IEEE Symposium on Parallel and Distributed Processing, Oct. 25-28.) ------------------------------------------------------------------------------- 8:00-10:00 am APPROACHES AND METHODS Chair: Michael Rowley, Intermetrics, USA "Is consistency needed in ditributed object-based systems?", Maarten Boasson, Hollands Signaal, The Netherlands (30 minutes) "A Methodology and Toolset for the Design of Parallel Embedded Systems," Devesh Bhatt, Vicraj Thomas, and John Shackleton, Honeywell Technology Center, USA (30 minutes) "A Modular Approach to Real-Time Synchronization," Masahiko Saito and Gul A. Agha, University of Illinois at Urbana-Champaign, USA (30 minutes) "Composing and Reusing Synchronization and Real-time Specifications," Mehmet Aksit and Lodewijk M.J. Bergmans, University of Twente, The Netherlands (30 minutes) ------------------------------------------------------------------------------- 10:00-10:30 am BREAK ------------------------------------------------------------------------------- 10:30-12:00 am LANGUAGE ISSUES Chair: Bruno Achauer, Uni Linz, Austria "Objects in Real-Time Systems: Issues for Language Implementors," Bruno Achauer, Uni Linz, Institut f. Informatik/Telekooperation, Austria (30 minutes) "Benefits of Type Inference for an Object-Oriented Real-Time Language," Jan Gustafsson, Kjell Post, Jukka Maki-Turja, and Ellus Brorsson, University of Malardalen, Sweden (30 minutes) "Preserving the Causal and Structural Properties of Real-Time Systems using Object Oriented Specifications in Cleopatra," Azer Bestavros, Boston University, USA (30 minutes) ------------------------------------------------------------------------------- 12:00-1:00 pm LUNCH ------------------------------------------------------------------------------- 1:00-3:30 pm REAL-TIME ISSUES Chair: Azer Bestavros, Boston University, USA "Real-time Scheduling and Object Technologies," Harold Forbes and Karsten Schwan, Georgia Institute of Technology, USA (30 minutes) "Checking Timing Constraints in Distributed Object-Oriented Programs," M. Gergeleit and H. Streich, GMD - German National Research Center for Information Technology, J. Kaiser, University of Ulm, Germany (30 minutes) "Integration of Functional and Performance Verification in an Object-Oriented Framework," J. C. Browne, University of Texas at Austin, USA (30 minutes) "Real-Time Persistent Data Management in Ada95 using Storage Managers," Michael Rowley, Intermetrics, USA (30 minutes) "The Emergent Approach to Object Allocation in Computational Field," Minoru Uehara, Toyo University, Japan (30 minutes) ------------------------------------------------------------------------------- 3:30-4:00 pm BREAK ------------------------------------------------------------------------------- 4:00-5:30 pm REAL-TIME TECHNIQUES AND TOOLS Chair: Gul A. Agha, University of Illinois at Urbana-Champaign, USA "Metrics and Techniques for Exploiting Concurrency in Object-Based Real-Time Systems," Lonnie R. Welch, New Jersey Institute of Technology, USA (20 minutes) "Active Real-Time Objects in Ada," Mike Masters, Naval Surface Warfare Center, USA (20 minutes) "A Taxonomy for Distributed Object-Oriented Real-time Systems," Dieter K. Hammer and Onno S. van Roosmalen, Eindhoven University of Technology, The Netherlands Lonnie R. Welch, New Jersey Institute of Technology, USA (20 minutes) "PLENARY DISCUSSION OF REAL-TIME ISSUES" Discussion Leader: Devesh Bhatt, Honeywell Technology Center, USA (30 minutes) ------------------------------------------------------------------------------- 5:30-5:45 pm BREAK ------------------------------------------------------------------------------- 5:45-7:15 pm RUN-TIME AND APPLICATION ISSUES Chair: Mike Masters, Naval Surface Warfare Center, USA "High-Level Dynamic Memory Management for Object-Oriented Real-Time Systems," Kelvin Nilsen, Iowa State University, USA (30 minutes) "On the Development of Hard Real-Time Software for On-Board Control Systems," Tullio Vardanega, European Space Research and Technology Centre, Netherlands (30 minutes) "WORKSHOP SUMMARY AND DISCUSSION OF FUTURE DIRECTIONS," by the session chairs and the workshop chairs Discussion Leader: Maarten Boasson, Hollands Signaal, The Netherlands (30 minutes) ------------------------------------------------------------------------------- If you would like additional information about OORTS, please contact the workshop organizers: Lonnie R. Welch Dept. of Computer and Information Science New Jersey Institute of Technology University Heights Newark, NJ 07102 Vox: (201)-596-5683 / Fax: (201)-596-5777 Internet: welch@vienna.njit.edu Dieter K. Hammer Dept. of Mathematics and Computing Science Eindhoven University of Technology P. O. Box 513 NL-5600 MB Eindhoven The Netherlands Vox: +31-(0)40-474416 / Fax: +31-(0)40-463992 Internet: hammer@win.tue.nl ------------------------------------------------------------------------------ Message 3; Postmarked Tue Oct 17 19:40:55 1995 Return-Path: Received: from meter.eng.uci.edu by cs.bu.edu (8.6.10/Spike-2.1) id TAA08028; Tue, 17 Oct 1995 19:40:46 -0400 Received: from balboa.eng.uci.edu by meter.eng.uci.edu (8.7) id QAA13257; Tue, 17 Oct 1995 16:41:37 -0700 (PDT) From: Phillip C-Y Sheu Received: by balboa.eng.uci.edu (8.6.12) id QAA20115; Tue, 17 Oct 1995 16:41:35 -0700 Date: Tue, 17 Oct 1995 16:41:35 -0700 Message-Id: <199510172341.QAA20115@balboa.eng.uci.edu> To: IEEE-RTTC@cs.bu.edu Subject: WORDS96: Call for papers Second International Workshop on Object-oriented Real-time Dependable Systems (WORDS 96) February 1-2, 1996 Surf & Sand Hotel (Tentative) Laguna Beach, California, U.S.A. Sponsored by: IEEE Computer Society TC on Distributed Processing IEEE Orange County Section THEME Following the success of the first WORDS workshop held in 1994, this workshop continues its theme in integrating three computer system engineering technologies (CSETs): Object-oriented CSET, Real-time CSET, and Dependable CSET. For inclusion in the workshop program, contributions that present significant advances in integrating any two of the three component technology fields are invited. Industrial applications such as multimedia interactive services that facilitate such integrations are also encouraged to be addressed. The workshop is intended to be a forum for substantial exchange of newly recognized research issues, advanced promising formulations and research progress reports which may be of conceptual, theoretical, innovative design, or experimental nature, and represent technological or scientific advances. As such, the workshop will have a limited number of participants, probably not exceeding 50. TOPICS OF INTEREST Topics related to at least two of the three CSET's (object-oriented CSET, real-time CSET, and dependable CSET) are of interest to the Workshop. Some example topics are: - Object-oriented real-time system requirement and specification - Integration of time into formal object models - Tools for structuring active and/or real-time objects - OS support for object-oriented systems with real-time or dependability requirements - System resource allocation for real-time or depend- able objects - Testing and evaluation of temporal and dependability properties - Database architecture for real-time or highly- dependable services - Multimedia applications - Object-oriented, real-time simulations - Experience on automobile, avionics, industrial and medical applications Other related issues that are important to the design and implementation of object-oriented real-time dependable sys- tems are all welcome. PAPER SUBMISSIONS Position papers are solicited from potential par- ticipants of this workshop. Papers must be written in English and printed using at least 11-point type and 1-1/2 line spacing. (1) Papers from potential participants who are interested in detailed presentation of research results may be up to 15 pages in manuscript, including figures. (2) Potential participants who prefer to serve as panelists or commentators may submit position papers of 1 - 3 page length. Authors are requested to submit five hard copies of their manuscript, and also email the abstract and the full addresses of the author(s), before December 1, 1995 to: Prof. Phillip C-Y Sheu Department of Electrical and Computer Engineering University of California Irvine, CA 92717, USA +1-714-824-2660 +1-714-824-2321 (fax) sheu@ece.uci.edu Authors will be notified of the program committee deci- sion by December 15, 1995. The revised copy for inclusion in the preliminary proceedings (not to be treated as an official publication but rather a collection of working papers) to be distributed at the workshop will be due January 15, 1996. The final camera-ready copy for the IEEE Workshop Proceedings will be due 3 weeks after the the workshop. We expect that the proceedings will be printed by April 30, 1996. Proposal for Panel Sessions are also solicited. WORKSHOP GENERAL CHAIR Kane Kim University of California, Irvine U.S.A. kane@ece.uci.edu PROGRAM CO-CHAIRS Phillip C-Y Sheu Edgar Nett University of California, Irvine GMD U.S.A. Germany sheu@ece.uci.edu nett@gmd.de LOCAL-ARRANGEMENTS CO-CHAIRS: K.J. Lin, University of California at Irvine, USA Eltefaat Shokri, SoHaR, USA PUBLICITY COMMITTEE CO-CHAIRS: Larry Peterson, USN NRaD, USA Charles Jung, IBM, Boca Raton, USA PROGRAM COMMITTEE Alan Burns, York University, U.K. Jen-Yao Chung, IBM, T.J. Watson, USA Michael Gien, Chorus Systems, France Katsumi Kawano, Hitachi, Japan Moon H. Kim, Konkuk University, Korea Hermann Kopetz, Technische Universitat Wien, Austria Tom Lawrence, USAF Rome Laboratory, USA Insup Lee, University of Pennsylvania, USA James Lee, ITRI, Taiwan K.J. Lin, University of California at Irvine, USA W. L. McCoy, USN NSWC, USA C.J. Paul, IBM, Austin, USA Ray Paul, Office of the Under Secretary of Defense, USA Santosh Shrivastava, University of Newcastle upon Tyne, England Richard Soley, OMT, USA Hide Tokuda, Keio University, Japan Susan Urban, Arizona State University, USA Doug Wells, OSF, USA ------------------------------------------------------------------------------ Message 4; Postmarked Mon Oct 2 20:40:28 1995 From: toda@etlca0.etl.go.jp (Kenji Toda) Subject: Advance Program & Information on RTCSA95, Japan Content-Length: 19586 =============== ADVANCE PROGRAM =============== Second International Workshop on Real-Time Computing Systems and Applications (RTCSA'95) Held Jointly with Youth Forum in Computer Science and Engineering (YUFORIC) October 25-27, 1995 Kitashinkan Hall, Keio Univ. Tokyo, Japan -------------------- October 24 (Tuesday) 17:00 Registration at the Art Hotels Ohmori -- 19:00 -------------------- October 25 (Wednesday) RTCSA'95 8:15 Registration at Kitashinkan Hall, Keio Univ. 9:00 Opening Remarks Mario Tokoro (Keio Univ., Japan) Kane Kim (UC Irvine, USA) Kern Koh (Seoul National Univ., Korea) Kenji Toda (ETL, Japan) 9:15 Invited Talk 1 "The Many Faces of Multi-Level Real-Time Scheduling" Jack Stankovic (Univ. of Massachusetts, USA) 9:55 Session 1: Caches and Storage Management "The Impact of Extrinsic Cache Performance on Predictability of Real-Time Systems" Jose Vicente Busquets-Mataix and Juan Jose Serrano-Martin (Universidad Politecnica de Valencia, Spain) "Real-Time Aspects of Cluster Based Caches" (short) O. Hammami (Univ. of Aizu, Japan) "An Algorithm with Constant Execution Time for Dynamic Storage Allocation" (short) Takeshi Ogasawara (IBM Japan, Japan) 10:50 Break 11:05 Session 2: Networks and Communication I "A Bandwidth Reallocation Scheme for Ethernet-Based Real-Time Communication" Junghoon Lee and Heonshik Shin (Seoul National Univ., Korea) "The Effect of Different Packet Size in a Time-Token Protocol Network that Supports Real-Time Applications" Joseph K. Y. Ng (Hong Kong Baptist Univ, Hong Kong) "Performance Analysis of Real-Time Message Delivery in FDDI Networks" P. H. H. Tsang, J. Ng, E. Chan, and C. H. Lee (City Univ. of Hong Kong, Hong Kong) 12:20 Lunch 13:40 Invited Talk 2 "Real-Time Database Systems: Present and Future" Sang Hyuk Son (Univ. of Virginia, USA) 14:20 Session 3: Scheduling I "Real-Time Scheduling of Tasks that Contain the External Blocking Intervals" In-Guk Kim (Dankook Univ., Korea), Kyung-Hee Choi, Seung-Kyu Park, Dong-Yoon Kim, and Man-Pyo Hong (Ajou Univ., Korea) "Scheduling Real-Time Transactions with Dynamic Values: A Performance Evaluation" Shin-Mu Tseng (National Chiao Tung Univ., ROC), Y. H. Chin (National Tsing Hua Univ., ROC), and Wei-Pang Yang (National Chiao Tung Univ., ROC) "A Soft Aperiodic Task Scheduling Algorithm in Dynamic-Priority Systems" (short) Sungyoung Lee, Hyungill Kim (Kyunghee Univ., Korea), and Jongwon Lee (Korea Telecom, Korea) "A Generalized Utilization Bound Test for Fixed-Priority Real-Time Scheduling" (short) Dong-Won Park (PaiChai Univ., Korea), Swaminathan Natarajan (Xerox Corp, USA), Arkady Kanevsky (MITRE Corp., USA), and Myung Jun Kim (Chungbuk National Univ., Korea) 15:40 Break 15:55 Session 4: Operating Systems "A Timeliness-Guranteed Kernel Model -- DREAM Kernel -- and Implementation Techniques" K. H. (Kane) Kim, Luiz Bacellar, Yuseok Kim, Chittur Subbaraman, Hankil Yoon (UC Irvine, USA), Jungguk Kim (HUFS, Korea), and Kee-Wook Rim (ETRI, Korea) "Experiences with Building a Continuous Media Application on Real-Time Mach" Hiroshi Tezuka (Real World Computing Partnership, Japan) and Tatsuo Nakajima (JAIST, Japan) "Dynamic Code Binding for Scalable Operating System in Distributed Real-Time Systems" (short) Boo-Geum Jung, Young-Jun Cha, Hyung-Hwan Kim, Sung-Ik Jun, and Ju-Hyun Cho (ETRI, Korea) 17:00 Break 17:15 Session 5: Databases "Virtual Deadline Assignment in Distributed Real-time Database Systems" Victor C. S. Lee, Kam-yiu Lam, and Sheung-lun Hung (City Univ. of Hong Kong, Hong Kong) "Object-Oriented Design of Main-Memory DBMS for Real-Time Applications" S. K. Cha, B. D. Park, S. J. Lee, S. H. Song, J. H. Park (Seoul National Univ., Korea), J. S. Lee, S. Y. Park, D. Y. Hur (ETRI, Korea), and G. B. Kim (Pohang Iron & Steel Company, Korea) "Performance Evaluation of a Firm Real-Time DataBase System" Stuart Shih, Young-Kuk Kim, and Sang H. Son (Univ. of Virginia, USA) "Real-Time Mobile Data Management Using a Minimal MMDB" (short) Eun-Hee Hyun and Sung-Hee Kim (ETRI, Korea) 18:45 Reception -- 19:20 -------------------- October 26 (Thursday) RTCSA'95 8:15 Registration at Kitashinkan Hall, Keio Univ. 9:00 Invited Talk 3 "Fundamental Conflicts in the Design of Real-Time Protocols" Herman Kopetz (Technical Univ. of Vienna, Austria) 9:40 Session 6: Systems and Architectures "Issues in Using Heterogeneous HPC Systems for Embedded Real Time Signal Processing Applications" Prashanth B. Bhat, Young W. Lim, and Viktor K. Prasanna (Univ. of Southern California, USA) "Constructing Distributed Real-Time Systems with DROL Real-Time Objects" Kazunori Takashio (The Univ. of Electro-Communications, Japan), Hidehisa Shitomi (Keio Univ., Japan), and Mario Tokoro (Keio Univ./Sony CSL, Japan) "Performance Comparison of Real-Time Architectures Using Simulation" Heejo Lee (Pohang Univ. of Sci. and Tech., Korea), Kenji Toda (ETL, Japan), Jong Kim (Pohang Univ. of Sci. and Tech., Korea), Kenji Nishida, Eiichi Takahashi, and Yoshinori Yamaguchi (ETL, Japan) 10:55 Break 11:10 Session 7: Predictability Enhancements "Real-Time Scalability of Nested Spin Locks" Hiroaki Takada and Ken Sakamura (Univ. of Tokyo, Japan) "The Generated Order Preserving Real-Time Garbage Collection" Hiroshi Koide (The Univ. of Electro-Communications, Japan) "Improved Performance Model of a Real-Time Software Element: The Producer-Consumer" (short) Carlos Juiz and Ramon Puigjaner (Universitat de les Illes Balears, Spain) 12:15 Lunch 13:40 Invited Talk 4 "The Middleware Services for Industrial Computer Systems" Morikazu Takegaki (Mitsubishi Elec. Corp., Japan) 14:20 Session 8: Formal Methods and Fault Tolerance "Comparing Formal Specifications by Measuring" J. van Katwijk and W. J. Toetenel (Delft Univ. of Technology, The Netherlands) "Verification System for Real-Time Specification Based on Extended Real-Time Logic" (short) Satoshi Yamane (Shimane Univ., Japan) "A New Fault-Tolerant Scheduling Technique for Real-Time Multiprocessor Systems" Tatsuhiro Tsuchiya, Yoshiaki Kakuda, and Tohru Kikuno (Osaka Univ., Japan) "Efficient NMRCD Scheme for Fault Tolerance in Responsive Systems" (short) Christopher P. Fuhrman, Sailesh Chutani, and Henri J. Nussbaumer (Swiss Federal Inst. of Technology, Switzerland) 15:40 Break 15:55 Session 9: Scheduling II "Allocation and Scheduling of Real-Time Periodic Tasks with Relative Timing Constraints" Sheng-Tzong Cheng and Ashok K. Agrawala (Univ. of Maryland, USA) "Optimal Server Allocation for Real Time Computing Systems with Bursty Priority Jobs" Sungcheol Hong (Korea Telecom, Korea) "A Processor Reservation System Supporting Dynamic QOS Control" Hiroshi Fujita, Tatsuo Nakajima, and Hiroshi Tezuka (JAIST, Japan) "Scheduling Hard-Realtime Parallel Tasks onto the Processor Network with Wrapped Mesh Topology" Yasuhiro Kokusho (Fujitsu Lab., Japan) and Norihisa Doi (Keio Univ., Japan) 17:35 Break 17:50 Session 10: Networks and Communications II "Real-Time Bus and Task Allocation for a Multiprocessor Based Programmable Controller" Gab Seon Rho and W. H. Kwon (Seoul National Univ., Korea) "Real-Time Communication in Plant Monitoring/Controlling Systems with ATM Networks" Ichiro Mizunuma, Satoshi Horiike, and Morikazu Takegaki (Mitsubishi Elec. Corp, Japan) "An Application of Real-Time IPC Controller Based ATM Cell" (short) Hee-Sook Park, S. J. Moon, H. G. Yeo, and K. S. Song (ETRI, Korea) 19:00 Banquet -- 21:00 -------------------- October 27 (Friday) YUFORIC + RTCSA'95 8:15 Registration at Kitashinkan Hall, Keio Univ. 9:00 Greeting from YUFORIC Organizer Yoshiaki Kakuda (Osaka Univ., Japan) 9:05 Invited Talk 5 "Operating System Support for Continuous Media Applications -- RT-Mach Extensions" Hideyuki Tokuda (Keio Univ., Japan / CMU, USA) 9:45 Panel Session "Future Trends in Real-Time Networking" Chair: Heonshik Shin (Seoul National Univ., Korea) 11:15 Technical Presentations -- 15:10 15:50 Visit to NTT Kasumigaseki Communication Center -- 17:00 ======================================================================== RTCSA'95/YUFORIC REGISTRATION FORM October 25-27, 1995 Kitashinkan Hall, Keio Univ. Tokyo, Japan To register, please FAX or MAIL this form to: RTCSA95 Registration, c/o TRON Association, Katsuta Bldg. 5F, 1-3-39 Mita, Minato-ku, Tokyo 108, JAPAN (FAX: +81-3-3454-3224). (Please check appropriate registration) RTCSA'95 + YUFORIC __ YUFORIC __ (Please type or print) Choose your title: Prof. Dr. Mr. Ms. Name (Last, First, MI): Affiliation: Address: City/State/ZIP: Country: Phone: FAX: E-mail: IEEE/IEEE CS/IEICE/IPSJ/KISS/TRON Association Member Number: ------------------------------ REGISTRATION FEES RTCSA95 + YUFORIC (October 25-27): Advance (before October 7) Late (after October 8) Member: 34,000Yen (or US$350) 38,000Yen (or US$400) Non-member: 43,000Yen (or US$450) 48,000Yen (or US$500) Full-time student member: 10,000Yen (or US$100) 15,000Yen (or US$150) Full-time student: 12,000Yen (or US$120) 18,000Yen (or US$180) * Member fees apply to IEEE/IEEE CS/IEICE/IPSJ/KISS/TRON Association Member. * The registration except full-time students includes a copy of proceedings, coffee-breaks, one reception, and one banquet. A banquet is not included in the full-time student registration. Students who wish to attend a banquet must purchase a banquet ticket. * Advance registrations must be received until October 7th. YUFORIC only (October 27): Advance (before October 7) Late (after October 8) Member: 5,000Yen (or US$52) 7,000Yen (or US$73) Non-member: 7,000Yen (or US$73) 9,000Yen (or US$94) Full-time student member: complementary complementary Full-time student: 2,000Yen (or US$21) 2,500Yen (or US$26) * Member fees apply to IEEE and IEEE CS members only. * The registration includes coffee-breaks. * Advance registrations must be received until October 7th. BANQUET: I wish to purchase ( ) banquet tickets at 6000Yen (or US$60) each, to a total of: * The registration except full-time students includes a banquet. TOTAL: I am enclosing the total of: VISIT TO NTT KASUMIGASEKI COMMUNICATION CENTER: I wish to visit NTT Kasumigaseki Communication Center: Yes No * Due to the limit of the number of visitors, we may not be able to accept all the applications. ------------------------------ Please attach the exact payment in one of the following forms. 1. A check payable on a Japanese bank and written to "RTCSA95". 2. A proof of direct transfer to Sumitomo Bank with the following. Account Name RTCSA95 Bank Name Sumitomo Bank Branch Name Shiba Branch Account No. Ordinary Acct. No.598721 3. Credit card payment (VISA or MasterCard only) Total: Yen VISA __ MasterCard __ Credit Card Number: Expiration Date: Card Holder's Name: Signature: * If you select credit card payment, you must pay in Japanese Yen. * We recommend the attendances from Japan to pay with direct bank transfer. For any questions, send E-mail to RTCSA'95 Registration Chair, Hiroaki Takada (E-mail: hiro@is.s.u-tokyo.ac.jp) or send fax to RTCSA95 Registration, c/o TRON Association (FAX: +81-3-3454-3224). ======================================================================== RTCSA'95/YUFORIC HOTEL RESERVATION FORM The Art Hotels Ohmori Tokyo, Japan To register with the hotel, please FAX or MAIL this form to: The Art Hotels Ohmori, JAPAN (FAX: +81-3-3766-7201, TEL: +81-3-3766-7001). The RTCSA'95/YUFORIC special rates are 9000Yen/15000Yen for a single/twin room per night (plus local tax (3%); breakfast and service charges included). These rates are in effect three days before through two days after the meeting. There is a cutoff date of October 7th, after which the hotel is not obligated to accommodate guests at this rate. * Bus service will be arranged from/to the Art Hotels Ohmori to/from Kitashinkan Hall, Keio Univ. during the workshop period. (Please type or print) ----------------------------cut here------------------------------------ ART HOTELS OHMORI ROOM RESERVATION (RTCSA'95/YUFORIC) +------------------+----------------------------------------------------+ |GUEST NAME | | |(Last, First, MI) | | +------------------+----------------------------------------------------+ |ROOM TYPE | Single | |(circle or mark) | Twin | +------------------+----------------------------------------------------+ |NO. OF PERSONS | | | | | +------------------+----------------------------------------------------+ |ARRIVAL DATE | | | | | +------------------+----------------------------------------------------+ |DEPARTURE DATE | | | | | +------------------+----------------------------------------------------+ |TEL | | |FAX | | +------------------+----------------------------------------------------+ |AFFILIATION | | |ADDRESS | | |(City/State/ZIP) | | |(Country) | | +------------------+----------------------------------------------------+ ART HOTELS OHMORI 6-19-3 MINAMIOHI SHINAGAWA-KU TOKYO 140, JAPAN TEL +81-3-3766-7001 (03-3766-7001 in Japan) FAX +81-3-3766-7201 (03-3766-7201 in Japan) ======================================================================== GENERAL INFORMATION YUFORIC: The aim of Youth Forum in Computer Science and Engineering (YUFORIC) is to provide an opportunity for students and young researchers to come together and exchange ideas to further develop their studies. The seminar will provide a forum for stimulated exchanges between students and young researchers with an aim to advancing future research activities. As well students participants will have the extra opportunity to experience an inside view of the present research carried out in the professional community. The second YUFORIC is held jointly with RTCSA'95 to discuss the common theme real-time technology and applications. NTT Kasumigaseki Communication Center is a showroom of NTT's advanced tele-communication technologies and will show you the new styled tele-communication of the coming multimedia-era with some examples and applications. It consists of the Public Zone, Personal Zone, Business Zone, and the R&D Zone. English and Japanese guidance courses are available. Passport & Visa: Every foreign visitor entering Japan must possess a valid passport and visa. Contact the nearest Japanese diplomatic or consular mission abroad for further information. Currency: The unit of currency is Japanese Yen. There are banknotes for 1000, 5000, and 10000 Yen and coins is denominations of 1, 5, 10, 50, 100, and 500 Yen. Exchange rates rapidly fluctuate. One US dollar is equivalent to 95 - 100 Yen as of September 1995. Transportation: From New Tokyo International Airport (Narita), take the N'EX (Narita Express) of JR line or the Keisei Skyliner express train. Change trains at the Tokyo Station (N'EX) or the Ueno Station (Keisei) to JR Keihin-Tohoku Line. Take off the train at the Ohmori Station (for the Art Hotels Ohmori) or at the Tamachi Station (for Kitashinkan Hall, Keio Univ.). With either route, it takes about two hours from the airport to the hotel. We do not recommend you to use a taxi from the airport, because it is quite expensive (about 25,000 - 30,000 Yen). ======================================================================== RTCSA'95 Organization --------------------- General Co-Chairs: Mario Tokoro (Keio Univ./Sony CSL, Japan) Kane Kim (UC Irvine, USA) Program Co-Chairs: Kern Koh (Seoul National Univ., Korea) Kenji Toda (ETL, Japan) Program Committee: Tadashi Ae (Hiroshima Univ., Japan) Arbee Chen (Tsing Hua Univ., Taiwan) Dieter K. Hammer (Eindhoven Univ. of Techn., The Netherlands) Shing-Tsaan Huang (Tsing Hua Univ., Taiwan) Yoshiaki Kakuda (Osaka Univ., Japan) Moon Hae Kim (Konkuk Univ., Korea) Jong Kim (POSTECH, Korea) Hermann Kopetz (Tech. Univ. of Vienna, Austria) Insup Lee (Univ. of Pennsylvania, USA) Jane Liu (Univ. of Illinois, USA) Sang Lyul Min (Seoul National Univ., Korea) Al Mok (Univ. of Texas at Austin, USA) Joseph Kee-Yin Ng (Hong Kong Baptist Univ., Hong Kong) Seung-Kyu Park (Ajou Univ., Korea) Lui Sha (CMU, USA) Alan Shaw (Univ. of Washington, USA) Kang G. Shin (Univ. of Michigan, USA) Sang Hyuk Son (Univ. of Virginia, USA) John A. Stankovic (Univ. of Massachusetts, USA) Ichiro Suzuki (Univ. of Wisconsin Milwaukee, USA) Morikazu Takegaki (Mitsubishi Elec. Corp., Japan) Hideyuki Tokuda (Keio Univ., Japan /CMU, USA) Tetsuo Wasano (ATRI, Japan) Lonnie Welch (NJIT, USA) Seung Min Yang (Soongsil Univ., Korea) Publicity Co-Chairs: Nobuo Saito (Keio Univ., Japan) Seog Park (Sogang Univ., Korea) Registration Chair: Hiroaki Takada (Univ. of Tokyo, Japan) Local Arrangements Chair: Eiichi Takahashi (ETL, Japan) YUFORIC Chair: Yoshiaki Kakuda (Osaka Univ., Japan) Advisory Committee: Chair: Heonshik Shin (Seoul National Univ., Korea) Wook Hyun Kwon (Seoul National Univ., Korea) Takashi Nodera (Keio Univ., Japan) Ken Sakamura (Univ. of Tokyo, Japan) Yoshinori Yamaguchi (ETL, Japan) ======================================================================== YUFORIC Organization --------------------- YUFORIC Organizer: Yoshiaki Kakuda (Osaka Univ., Japan) Program Committee: Masahito Hirakawa, (Hiroshima Univ., Japan) Kenji Ishida, (Hiroshima Prefectural Univ., Japan) Chair: Yoshiaki Kakuda, (Osaka Univ., Japan) Hermann Kopetz, (Tech. Univ. of Vienna, Austria) Miroslaw Malek, (Humboldt Univ., Germany) Shuichi Matsumoto, (KDD, Japan) Al Mok, (Univ. of Texas at Austin, USA) Morikazu Takegaki, (Mitsubishi Elec. Corp., Japan) Kenji Toda, (ETL, Japan) Mario Tokoro (Keio Univ./Sony CSL, Japan) Hideyuki Tokuda, (Keio Univ., Japan / CMU, USA) Tetsuo Wasano, (ATRI, Japan) Tomohiro Yoneda, (Tokyo Inst. of Technology, Japan) ======================================================================== RTCSA'95 Home Page: For further information, access the RTCSA'95 Home Page at "http://tron.is.s.u-tokyo.ac.jp/RTCSA95/". ------------------------------------------------------------------------------ <<<<<<<<<<<<<<<<<<<* END OF THE IEEE-CS TC-RTS NEWSLETTER *>>>>>>>>>>>>>>>>>>> ------------------------------------------------------------------------------ The TC-RTS repository is maintained by Azer Bestavros at Boston University WWW Home Page of the TC-RTS is at: http://cs-www.bu.edu/pub/ieee-rts/Home.html Internet address for anonymous FTP to the TC-RTS repository is: cs-ftp.bu.edu Contributions to this forum should be sent via E-mail to: IEEE-RTTC@cs.bu.edu Requests / inquiries should be sent via E-mail to: IEEE-RTTC-request@cs.bu.edu ------------------------------------------------------------------------------